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RT7302 ? ds7302-01 december 2013 www.richtek.com 1 ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. primary-side -regulation dimma ble led driver controller with active pfc general description the RT7302 is a constant current led driver with active power factor correction. it supports high power factor across a wide range of line voltages, and it drives the converter in the quasi-resonant (qr) mode to achieve higher efficiency. by using primary side regulation (psr), the RT7302 controls the output current accurately without a shunt regulator and an opto-coupler at the secondary side, reducing the external component count, the cost, and the volume of the driver board. the RT7302 is designed to be compatible with pwm dimming. the output current can be modulated by the duty ratio of the external pwm dimming signal. an in-house design high voltage (hv) start-up device is integrated in the RT7302 to minimize the power loss and shorten the start-up time. the RT7302 embeds comprehensive protection functions for robust designs, including led open-circuit protection, led short-circuit protection, output diode short-circuit protection, vdd under-voltage lockout (uvlo), vdd over-voltage protection (vdd ovp), over-temperature protection (otp), and cycle-by-cycle current limitation. features ? ? ? ? ? tight led current regulation ? ? ? ? ? no opto-coupler and tl431 required ? ? ? ? ? power factor correction (pfc) ? ? ? ? ? compatible with pwm dimming ? ? ? ? ? built-in hv start-up device ? ? ? ? ? quasi-resonant ? ? ? ? ? maximum/minimum switching frequency clamping ? ? ? ? ? input voltage feed-forward compensation ? ? ? ? ? maximum/minimum on-time limitation ? ? ? ? ? wide vdd voltage range (up to 25v) ? ? ? ? ? multiple protection features ? ? ? ? ? led open-circuit protection ? ? ? ? ? led short-circuit protection ? ? ? ? ? output diode short-circuit protection ? ? ? ? ? vdd under-voltage lockout ? ? ? ? ? vdd over-voltage protection ? ? ? ? ? over-temperature protection ? ? ? ? ? cycle-by-cycle current limit ? ? ? ? ? rohs compliant and halogen free applications ? ac/dc led lighting driver flyback converter buck-boost converter simplified application circuit v out+ mult comp gnd gd cs vdd RT7302 v out- hv d out tx1 r pc r cs d aux c vdd r zcd1 r zcd2 zcd r hv r m1 r m2 c comp c sin line neutral bd c out q1 v out- mult comp gnd gd cs vdd RT7302 v out+ hv d out tx1 r pc r cs d aux c vdd r zcd1 r zcd2 zcd r hv r m1 r m2 c comp c sin line neutral bd c out q1
RT7302 2 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1 hv high voltage input for startup. 2 gnd ground of the controller. 3 comp compensation node. output of the internal trans-conductance amplifier. 4 mult input for line voltage signal. this pin is used to sense the line voltage by resistor divider to achieve dimming function. 5 zcd zero current detection input. th is pin is used to sense the voltage at auxiliary winding of the transformer for detecting demagnetization time of the magnetizing inductance. 6 cs current sense input. connect this pin to the current sense resistor. 7 gd gate driver output for external power mosfet. 8 vdd supply voltage (v dd ) input. the controller will be enabled when v dd exceeds v th_on and disabled when v dd is lower than v th_off . marking information ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. pin configurations (top view) sop-8 RT7302 package type s : sop-8 lead plating system g : green (halogen free and pb free) hv gnd comp mult vdd gd zcd cs 2 3 4 5 6 7 8 RT7302 gsymdnn RT7302gs : product number ymdnn : date code
RT7302 3 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram starter circuit output diode short circuit protection comp under voltage lockout (16v/9v) vdd over voltage protection zcd cs gd vdd gnd hv start-up control hv pwm control logic v clamp 13v r gd gate driver vdd ovp pwm + - + - constant on-time comparator current limit comparator v cs_cl 1v over temperature protection otp ramp generator constant current control l : open h : closed + - dimming comparator v mult_en / v mult_ds 150mv / 100mv valley detector clamping circuit mult knee detector sample and hold output over voltage protection leading edge blanking output ovp i cs knee v mult feed-forward compensation v mult
RT7302 4 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ?? in_pk on l_pk m vsin( )t i = l figure 2. inductor current of crm with constant on-time control if the input voltage is the output voltage of the full-bridge rectifier with sinusoidal input voltage (v in_pk x sin( )), the inductor peak current (i l_pk ) can be expressed as the following equation : when the converter operates in crm with constant on- time control, the envelope of the peak inductor current will follow the input voltage waveform with in-phase. thus, high power factor can be achieved, as shown in figure 2. i l_pk i q1_ds peak inductor current mosfet current v in input voltage i in_avg i dout average input current output diode current v q1_gs mosfet gate voltage operation critical-conduction mode (crm) with constant on-time control figure 1 shows a typical flyb ack converter with input voltage (v in ). when main switch q1 is turned on with a fixed on- time (t on ), the peak current (i l_pk ) of the magnetic inductor (l m ) can be calculated by the following equation : figure 1. typical flyback converter ? in l_pk on m v i = t l primary-side constant-current regulation the RT7302 needs no shunt regulator and opto-coupler at the secondary side to achieve the output current regulation. figure 3 shows several key waveforms of a conventional flyback converter in quasi-resonant (qr) mode, in which v aux is the voltage on the auxiliary winding of the transformer, t on is the conducting time of q1, t off is the conducting time of d out , t s is a single switching period, n p is the turns number of primary winding and n s is the turns number of secondary winding. when the secondary side current i dout drops to zero, a knee point on v aux can be detected and t off can be determined. the average output current (i out (t)) can be derived by : ?? ??? off out dout_pk s cs_pk off p sscs t(t) 1 i (t) = i (t) 2t(t) v (t) t(t) n 1 = 2t(t)n r in every switching cycle, the RT7302 detects the t off (t), v cs_pk (t) and t s (t) for the constant-current regulation loop. for regulating the dc current level of the average output current (i out (t)) at a programmed level (i out_cc ), the RT7302 regulates the t on to make the following equation true : ?? ? ?? ?? cc off cs_pk s average value (k ) t(t) of v (t) = 0.25v (typ.) t(t) therefore, the i out_cc is calculated by the following equation : ?? cc p out_cc scs k n 1 i = 2n r figure 3. key waveforms of a flyback converter v aux v in i q1 gd (v gs ) (v out + v f ) x n a / n s 0 0 v in x n a / n p i dout clamped by controller knee v ds t off t on t s d out tx1 c out + v out - r out i out q1 + i l l m v in
RT7302 5 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. voltage clamping circuit the RT7302 provides a voltage clamping circuit at zcd pin since the voltage on the auxiliary winding is negative when the main switch is turned on. the lowest voltage on zcd pin is clamped near zero to prevent the ic from being damaged by the negative voltage. meanwhile, the sourcing zcd current (i zcd_sh ), flowing through the upper resistor (r zcd1 ), is sampled and held to be a line-voltage-related signal for propagation delay compensation. the RT7302 embeds the programmable propagation delay compensation through cs pin. a sourcing current i cs (equal to i zcd_sh x k pc ) applies a voltage offset (i cs x r pc ) which is proportional to line voltage on cs to compensate the propagation delay effect. thus, the output current can be equal at high and low line voltage. quasi-resonant operation for improving converter's efficiency, the RT7302 detects valleys of the drain-to-source voltage (v ds ) of main switch and turns on it near the selected valley. for the valley detections, a pulse of the ? valley signal ? is generated after a 500ns (typ.) delay time which starts at which the voltage (v zcd ) on zcd pin goes down and reaches the voltage threshold (v zcdt , 0.4v typ.). during the rising of the v zcd , the v zcd must reach the voltage threshold (v zcda , 0.5v typ.). otherwise, no pulse of the ? valley signal ? is generated. moreover, if the timing when the falling v zcd reaches v zcdt is not later than a mask time (t mask , 2 s typ.) then the valley signal will be masked and regards as no valley, as shown in figure 4. figure 4. valley signal generating method figure 5 illustrates how valley signal triggers pwm. if no valley sign al is detected for a long time, the next pwm is triggered by a starter circuit at the end of the interval (t start , 130 s typ.) which starts at the rising edge of the previous pwm signal. a blanking time (t s(min) , 8.5 s typ.), which starts at the rising edge of the previous pwm signal, limits minimum switching period. when the t s(min) interval is on-going, all of valley signals are not allowed to trigger the next pwm signal. after the end of the t s(min) interval, the coming valley will trigger the next pwm signal. if one or more valley signals are detected during the t s(min) interval and no valley is detected after the end of the t s(min) interval, the next pwm signal will be triggered automatically at the end of the t s(min) + 5 s (typ.). figure 5. pwm triggered method pwm t s(min) 5s valley signal pwm t s(min) valley signal pwm valley signal t s(min) pwm valley signal t start v zcd valley signal pwm 500ns t mask v zcda v zcdt
RT7302 6 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. hv start-up device an in-house design 500v start-up device is integrated in the RT7302 to minimize the power loss and shorten the start-up time. the hv start-up device will be turned on during start-up period and be turned off during normal operation. it guarantees fast start-up time and no power loss in this path during normal operation. a 10k resistor is recommended to be connected in series with hv pin. feed-forward compensation the mult pin is a high impedance input pin used to detect the line input voltage. a proper voltage divider and a capacitor should be applied to sense the rectified input voltage at the output of bridge diode rectifier. since the mult voltage is proportional to the rectified input voltage, it is used to generate a feed-forward signal, the peak of the mult voltage, to compensate the slope of the ramp, which is the non-inverting input of the constant on-time comparator. this function reduces the operating comp voltage range over full line input voltage range and extends the range of the allowed magnetize inductance. pwm dimming function pwm dimmable function is embedded in the RT7302. when the mult voltage (v mult ) < v mult_dis , the comp pin will become high impedance and the regulation loop operates according to the voltage (v comp ). the loop will keep operation with the previous condition. when v mult > v mult_en , the internal amplifier resumes controlling the v comp for the regulation loop to provide the constant output current. thus, the average output current is linearly proportional to the duty ratio of the pwm dimming signal protections led open-circuit protection in an event of output open circuit, the converter will be shut down to prevent being damaged, and it will be auto- restarted when the output is recovered. once the led is open, the output voltage and v zcd will rise. when the sample-and-hold zcd voltage (v zcd_sh ) exceeds its ov threshold (v zcd_ovp , 3.1v typ.), output ovp will be activated and the pwm output (gd pin) will be forced low to turn off the main switch. if the output is still open-circuit when the converter restarts, the converter will be shut down again. led short-circuit protection led short-circuit protection can be achieved by vdd uvlo and cycle-by-cycle current limitation. once led short- circuit failure occurs, v dd drops related to the output voltage. when the v dd is lower than falling uvlo threshold (v th_off , 9v typ.), the converter will be shut down and it will be auto-restarted when the output is recovered. output diode short-circuit protection when the output diode is damaged as short-circuit, the transformer will be led to magnetic saturation and the main switch will suffer from a high current stress. to avoid the above situation, an output diode short-circuit protection is built-in. when cs voltage v cs exceeds the threshold (v cs_sd 1.5 typ.) of the output diode short-circuit protection, the RT7302 will shut down the pwm output (gd pin) in few cycles to prevent the converter from damage. it will be auto-restarted when the failure condition is recovered. vdd under-voltage lockout (uvlo) and over-voltage protection(vdd ovp) the RT7302 will be enabled when vdd voltage (v dd ) exceeds rising uvlo threshold (v th_on , 16v typ.) and disabled when v dd is lower than falling uvlo threshold (v th_off , 9v typ.). when v dd exceeds its over-voltage threshold (v ovp , 27v typ.), the pwm output of the RT7302 is shut down. it will be auto-restarted when the v dd is recovered to a normal level. over-temperature protection (otp) the RT7302 provides an internal otp function to protect the controller itself from suffering thermal stress and permanent damage. it's not suggested to use the function as precise control of over temperature. once the junction temperature is higher than the otp threshold (t sd , 150 c typ.), the controller will shut down until the temperature cools down by 30 c (typ.). meanwhile, if v dd reaches falling uvlo threshold voltage (v th_off ), the controller will hiccup till the over-temperature condition is removed.
RT7302 7 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics (v dd = 15v, t a = 25 c, unless otherwise specification) absolute maximum ratings (note 1) ? hv to gnd ----------------------------------------------------------------------------------------------------------- ? 0.3v to 500v ? vdd to gnd --------------------------------------------------------------------------------------------------------- ? 0.3v to 30v ? gd to gnd ----------------------------------------------------------------------------------------------------------- ? 0.3v to 20v ? mult, cs, zcd, comp to gnd -------------------------------------------------------------------------------- ? 0.3v to 6v ? power dissipation, p d @ t a = 25 c sop-8 ----------------------------------------------------------------------------------------------------------------- 0.48w ? package thermal resistance (note 2) sop-8, ja ----------------------------------------------------------------------------------------------------------- 206.9 c/w ? junction temperature ---------------------------------------------------------------------------------------------- 150 c ? lead temperature (soldering, 10 sec.) ---------------------------- -------------------------------------------- 260 c ? storage temperature range ------------------------------------------------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (human body model) (exce pt hv pin) ----------------------------------------------------------------- 2kv mm (ma chine model) ---------------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) ? supply input voltage, v dd ---------------------------------------------------------------------------------------- 12v to 25v ? comp voltage, v comp -------------------------------------------------------------------------------------------- 0.7v to 4.3v (note 5) ? junction temperature range ------------------------------------------------------------------------------------- ? 40 c to 125 c parameter symbol test conditions min typ max unit hv start-up section hv start-up average current i hv_st v dd < v th_on , v hv = 100v 0.8 -- -- ma off state leakage current v dd = v th_on + 1v, v hv = 500v -- -- 2 ? a vdd supply current and protections section vdd ovp threshold voltage v ovp 25.5 27 28.5 v vdd ovp de-bounce time (note 6) -- 10 -- ? s rising uvlo threshold voltage v th_on 15 16 17 v falling uvlo threshold voltage v th_off 8 9 10 v operating supply current i dd_o p i zcd = 0, gd open -- -- 3.5 ma start-up current v dd = v th_on ? 1v -- -- 30 ? a zcd section lower clamp voltage i zcd = 0 to ? 2.5ma -- 0 0.3 v zcd ovp threshold voltage v zcd_ovp at the knee point (note 6) 2.8 3.1 3.4 v dimming control section enable threshold voltage v mult _en v mult rising -- 150 -- mv disable threshold voltage v mult _di s v mult falling -- 100 -- mv de-bounce time (note 6) -- 7 -- ? s
RT7302 8 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a low effective thermal conductivity two-layer test board per jedec 51-3. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. please refer to ? feed-forward compensation design ? in ? application information ? . note 6. guaranteed by design. parameter symbol test conditions min typ max unit constant current control section regulated factor for constant-current control k cc k cc = average value of (v cs_pk x t off / t s ) 0.245 0.25 0.255 v maximum comp voltage i co mp < 30 ? a 4.5 -- -- v maximum comp sourcing current i comp(max) v comp < 3.5v -- 62.5 -- ? a timing control section minimum on-time t on(min) i zcd = ? 150 ? a 2.2 2.7 3.2 ? s maximum on-time t on(max) 29 47 65 ? s minimum switching period t s(min) 7 8.5 10 ? s duration of starter t start at no valley detected 75 130 300 ? s current sense section blanking time t leb leb + propagation delay (note 6) 240 400 570 ns output diode short-circuit protection voltage threshold at cs v cs_sd shutdown when v cs > v cs_sd in 7 cycles. -- 1.5 -- v cs voltage threshold for peak current limitation v cs_cl 0.93 1.03 1.13 v propagation delay compensation factor k pc sourcing i cs = i zcd x k pc , i zcd = ? 150 ? a -- 0.02 -- a/a gate driver section gd voltage rising time t r c l = 1nf -- 60 80 ns gd voltage falling time t f c l = 1nf -- 40 70 ns gd output clamping voltage v clamp c l = 1nf -- 13 -- v internal gd pull low resistor r gd -- 40 -- k ? over-temperature protection section over-temperature threshold t sd (note 6) -- 150 -- ? c over-temperature threshold hysteresis t sd_hys (note 6) -- 30 -- ? c
RT7302 9 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit c vdd ( ? f) c comp ( ? f) c mult (nf) c zcd (pf) c cs (pf) r hv (k ? ) r m1 (m ? ) r m2 (k ? ) r gp (k ? ) r g ( ? ) r aux ( ? ) 22 1 1 22 4.7 (optional) 10 7.5 51 10 47 10 table 1. suggested component values buck-boost application circuit flyback application circuit + mult comp gnd gd cs vdd RT7302 v out hv d out tx1 r sn3 c sn2 d sn r sn1 c sn1 q1 r g r gp r pc r cs d aux r aux c vdd r zcd1 r zcd2 zcd c zcd r hv r m1 r m2 c comp c mult c sin r ntc f1 line neutral 1 4 3 2 7 6 8 5 bd c out - r sn2 c cs mult comp gnd gd cs vdd RT7302 hv d out tx1 q1 r g r gp r cs d aux r aux c vdd r zcd1 r zcd2 zcd c zcd r hv r m1 r m2 c comp c mult c sin r ntc f1 line neutral 1 4 3 2 7 6 8 5 bd c out + v out - r pc c cs
RT7302 10 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics i hv_st vs. temperature 0.80 1.00 1.20 1.40 1.60 1.80 2.00 -50 -25 0 25 50 75 100 125 temperature (c) i hv_st (ma) v ovp vs. temperature 26.0 26.4 26.8 27.2 27.6 28.0 -50 -25 0 25 50 75 100 125 temperature (c) v ovp (v) v th_off vs. temperature 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v th_off (v) i dd_op vs. temperature 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 -50 -25 0 25 50 75 100 125 temperature (c) i dd_op (ma) k cc vs. temperature 0.230 0.235 0.240 0.245 0.250 0.255 0.260 0.265 0.270 -50 -25 0 25 50 75 100 125 temperature (c) k cc (v) v th_on vs. temperature 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 -50 -25 0 25 50 75 100 125 temperature (c) v th_on (v)
RT7302 11 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. i comp(max) vs. temperature 30 40 50 60 70 80 90 100 -50 -25 0 25 50 75 100 125 temperature (c) i comp(max) ( a) t on(min) vs. temperature 2.0 2.2 2.4 2.6 2.8 3.0 -50 -25 0 25 50 75 100 125 temperature (c) t on(min) ( s) t start vs. temperature 90 100 110 120 130 140 150 -50 -25 0 25 50 75 100 125 temperature (c) t start ( s) v cs_sd vs. temperature 1.2 1.3 1.4 1.5 1.6 1.7 1.8 -50 -25 0 25 50 75 100 125 temperature (c) v cs_sd (v) v cs_cl vs. temperature 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -50 -25 0 25 50 75 100 125 temperature (c) v cs_cl (v) k pc vs. temperature 0.016 0.017 0.018 0.019 0.020 0.021 0.022 -50 -25 0 25 50 75 100 125 temperature (c) k pc (a/a)
RT7302 12 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information output current setting considering the conversion efficiency, the programmed dc level of the average output current (i out (t)) can be rewritten as : cc p out_cc tx1 scs sec_pk s tx1 pri_pk p k n 1 i = ctr 2n r i n ctr = in ?? ? ? in which ctr tx1 is the current transfer ratio of the transformer tx1, i sec_pk is the peak current of secondary side, and i pri_pk is the peak current of the primary side. ctr tx1 can be estimated to be 0.9. according to the above parameters, current sense resistor r cs can be determined as the following equation : cc p cs tx1 sout_cc k n 1 r= ctr 2n i ?? ? propagation delay compensation design the v cs deviation ( v cs ) caused by propagation delay effect can be derived as : in d cs cs m vtr v = l ?? ? ??? a cs pc in p zcd1 n 1 i = k v nr in which t d is the delay period which includes the propagation delay of the RT7302 and the turn-off transition of the main mosfet. the sourcing current from cs pin of the RT7302 (i cs ) can b e expressed as : where n a is the turns number of auxiliary winding. r pc can be designed by : ??? ? ? cs d cs zcd1 p pc cs m pc a vtrr n r = = ilkn minimum on-time setting the RT7302 limits a minimum on-time (t on(min) ) for each switching cycle. the t on(min) is a function of the sample- and-hold zcd current (i zcd_sh ) as following : ???? on(min) zcd_sh t i 375p sec a (typ.) in a zcd_sh zcd1 p vn i = rn ? ? i zcd_sh can be expressed as : thus, r zcd1 can be determined by : ? ? on(min) in a zcd1 p tv n r = (typ.) 375p n ac(max) a zcd1 p 2v n r > 2.5m n ? ? in addition, the current flowing out of zcd pin must be lower than 2.5ma (typ.). thus, the r zcd1 is also determined by : where the v ac(max) is maximum input ac voltage. output over-voltage protection setting output ovp is achieved by sensing the knee voltage on the auxiliary winging. it is recommended that output ov level (v out_ovp ) is set at 120% of nominal output voltage (v out ) . thus, r zcd1 and r zcd2 can be determined by the equation as : zcd2 a out s zcd1 zcd2 r n v 120% = 3.1v (typ.) nr r ?? ? ? feed-forward compensation design the comp voltage, v comp , can be derived from the following equations. v mult_pk is the peak voltage on the mult pin. gm ramp is the trans-conductance of the ramp generator, and its typical value is 2.5 a/v. c ramp is the capacitance of the ramp generator, and its typical value is 6.5pf. it is recommended to design v comp(min) = 1.2v. if the comp voltage is over its recommended operating range (0.7v to 4.3v), output current regulation may be affected. thus, the voltage divider resistors r m1 and r m2 can be determined according to the above parameters. ?? 2 on off mult_pk ramp on s ramp comp tt 1 vgmt 2t = c v ? ??? ?
RT7302 13 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. component range of typical value (tolerance < 30%) c vdd 10 ? f to 33 ? f c co mp 1 ? f to 4.7 ? f 10pf to 10nf (dimming) c mult 1nf to 100nf (non-dimming) c zcd 10pf to 22pf c cs nc to 22pf r hv 10k ? to 22k ? r m1 6.8m ? to 8.2m ? r m2 47k ? to 56k ? r gp 10k ? to 22k ? r g 10 ? to 47 ? r aux 10 ? to 100 ? table 2. suggested component values range thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 package, the thermal resistance, ja , is 206.9 c/ w on a standard jedec 51-3 two-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (206.9 c/w) = 0.48w for sop-8 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 6 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 6. derating curve of maximum power dissipation 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0255075100125 ambient temperature (c) maximum power dissipation (w) 1 two-layer pcb layout considerations a proper pcb layout can abate unknown noise interference and emi issue in the switching power supply. please refer to the guidelines when designing a pcb layout for switching power supply. ? the current path(1) from input capacitor, transformer, mosfet, r cs return to input capacitor is a high frequency current loop. the path(2) from gd pin, mosfet, r cs return to input capacitor is also a high frequency current loop. they must be as short as possible to decrease noise coupling and kept a space to other low voltage traces, such as ic control circuit paths, especially. besides, the path(3) between mosfet ground(b) and ic ground(d) is recommended to be as short as possible, too. ? the path(4) from rcd snubber circuit to mosfet is a high switching loop. keep it as small as possible. ? the path(5) from input capacitor to hv pin is a high voltage loop. keep a space from path(5) to other low voltage traces. ? it is good for reducing noise, output ripple and emi issue to separate ground traces of input capacitor(a), mosfet(b), auxiliary winding(c) and ic control circuit(d). finally, connect them together on input capacitor ground(a). the areas of these ground traces should be kept large.
RT7302 14 ds7302-01 december 2013 www.richtek.com ? copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 7. pcb layout guide ? placing bypass capacitor for abating noise on ic is highly recommended. the capacitors c mult , c comp , c zcd and c cs should be placed as close to the controller as possible. ? to minimize parasitic trace inductance and emi, minimize the area of the loop connecting the secondary winding, the output diode, and the output filter capacitor. in addition, apply sufficient copper area at the anode and cathode terminal of the diode for heat-sinking. it is recommended to apply a larger area at the quiet cathode terminal. a large anode area will induce high-frequency radiated emi. mult comp gnd gd cs vdd RT7302 hv zcd line neutral (4) (2) (b) (d) (3) (c) (5) (a) (1) input capacitor ground (a) ic ground (d) auxiliary ground (c) mosfet ground (b) trace trace trace c mult c comp c zcd c cs
RT7302 15 ds7302-01 december 2013 www.richtek.com richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050 outline dimension

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